As the DRAM device is highly integrated, it is required to obtain a capacity over 25 fF within a small cell dimension. Currently used ONO dielectric evolves limitations of manufacturing process.
Therefore, it is required an alternative technology for manufacturing capacitors using the high dielectrics capable of obtaining high capacity within the small cell dimension. gAs for the high dielectric film, there are (BaSr)TiO.sub.3 hereinafter "BST", BaTiO.sub.3 and SrTiO.sub.3.
FIG. 1 is a cross-sectional view for illustrating a method for fabricating a semiconductor memory device having a high dielectric layer as a capacitor insulating layer.
Referring to FIG. 1, an intermetal insulating layer 11 is formed on a semiconductor substrate 10 provided with a junction region 10a. The intermetal insulating layer 11 is etched to expose the junction region 10a, thereby forming a contact hole H. A contact plug 12 made of an impurity-doped polysilicon layer is formed within the contact hole H according to a known technique. A barrier metal layer 13 consisting of titanium 13a, titanium nitride 13b is deposited on the contact plug 12 and the intermetal insulating layer 11. The barrier metal layer 13 is patterned so that the barrier metal layer 13 is remained on and around the contact plug 12. A Pt metal layer for lower electrode is deposited on the intermetal insulating layer 11 in which the barrier metal layer 13 is formed, and then selected portions of the Pt metal layer is patterned and becomes a lower electrode 14. A high dielectric layer 15 is formed on the intermetal insulating layer 11 in which the lower electrode 14 is formed. A Pt metal layer for upper electrode is formed on the high dielectric layer 15 according to sputtering method. Next, selected portions of the high dielectric layer 15 and the Pt metal layer are patterned thereby forming an upper electrode 16.
In current giga DRAM devices, when the high dielectric layer 15 is deposited by thickness of 100.about.1000, distance between adjacent capacitors is approximately 0.12 .mu.m. Thus, aspect ratio between the respective capacitors is almost 2. Therefore, it is very difficult to deposit uniformly the Pt metal layer for forming the upper electrode on the high dielectric layer 15. In particular, the Pt metal layer for forming upper electrode is currently formed by the sputtering method having inferior characteristic of step coverage, therefore the Pt metal layer is deposited ununiformly on the high dielectric layer 15.
To solve the foregoing problem, there has been suggested another conventional method for forming the Pt metal layer, a MOCVD (metal organic chemical vapor deposition) method having excellent characteristic of step coverage.
When the Pt metal layer is deposited according to the MOCVD method, precursors such as Pt (C.sub.5 H.sub.7 O.sub.2).sub.2, (C.sub.5 H.sub.5) Pt (CH.sub.3).sub.3, (CH.sub.3 C.sub.5 H.sub.4) Pt (CH.sub.3).sub.3 and Pt(C.sub.5 HF.sub.6 O.sub.2).sub.2 are used. However, when the Pt metal layer is deposited by using those precursors, impurities such as carbon, oxygen and hydrogen consisting the precursors are remained at an interface between the Pt metal layer and the high dielectric layer. Those impurities form an electronic trap at the interface of the Pt metal layer and the high dielectric layer. Therefore, a leakage current is increased in the high dielectric layer thereby deteriorating electrical characteristics of the capacitor.